位置:51電子網 » 企業新聞

XC7K410T-1FFG676I高端物料專業供應商

發布時間:2019/8/27 11:47:00 訪問次數:53發布企業:深圳市恒意法科技有限公司

Xilinx 7 series FPGAs comprise three new FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series FPGAs include: Kintex-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs. Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs. 技術參數 Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory. 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering. High-performance SelectIO technology with support for DDR3 interfaces up to 1,866 Mb/s. High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces. A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors. DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering. Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter. Integrated block for PCI Express (PCIe), for up to x8 Gen3 Endpoint and Root Port designs. Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction. Low-cost, wire-bond, lidless flip-chip, and high signal integrity flipchip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option. Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power.

相關新聞

相關型號



燃烧的慾望怎么玩
河北快三玩法中奖规则 重庆时时龙虎和走势 新浪体育apk 幸运快三大小单双口诀 时时彩万位6码100% 快乐十分过滤软件下载 湖南幸运赛车 陕西快乐10分最常出现 大乐透复式14加2多少钱 足球手机即时比分 鳳凰彩票 上海时时乐杀号 微信捕鱼赚钱小游戏大全 欧洲足球指数即时比分 彩界九号独胆 心悦麻将辽宁版下载